The FireWorks™ (CWcomp02) is a 5-stage pipeline modified Harvard RISC architecture featuring a high-speed reprogramming interface and specific DSP instructions. This processor has instruction and data caches of configurable size. It can be configured to include (or not) instruction extensions, requiring additional hardware such as a 32-bit multiply or multiply/add with 64-bit result and saturation, barrel shifters, additional registers and adders/subtracters and a serial divider. External interrupt requests are supported. The CWcomp02 does not support exceptions for instructions or data.
The high-speed reprogramming interface can be used to load a program in the memory. In our prototypes it is typically connected FaceWorks™ (CWnet01), a local area network interface core. The prototypes can be controlled by a remote test program implemented with the Remote Access Library (RAL), a software package for building remote data exchange and control applications for cores connected using this infrastructure.
The FireWorks tool kit further features a GNU compiler and assembler (Gas), and tools to convert the executables (.elf files) in program memory models for simulation and implementation. The main features of Fireworks are the following:
32-bit data and instruction RISC architecture
5-stage pipeline
Configurable type and number of functional units
32-bit ALU
Configurable number of input and output ports
Optional Barrel shifter
Optional integer multiply or multiply/accumulate unit 32-bit operands / 64-bit result and saturation
Optional serial divider
1.31 DMIPS/MHz
CoreConnect™/OPB or AMBA®/AHB bus interface
High-speed reprogramming interface
GNU Binary Utilities
Networked programming and debugging tools
Program memory model generator from executable file
Small area, low power, multi purpose processor
Network interface allows easy debugging, monitoring and data exchange
Flexible Intellectual Property Blocks
